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Wafer Bumping Services

Wafer Bumping is an advanced wafer level packaging technology which uses solder bumps to form the interconnection between the integrated circuit (IC) and the package, and it is a replacement of wire bonding technology. This technology has the benefit of high density, good thermal dissipation and good electrical performance.
SPIL provides customers with both 200mm and 300mm wafer bumping services, including printed bump, plated bump and ball placement technology with eutectic, lead free and copper pillar materials.

APPLICATIONS
  Solder Bump/Ball Ball Placement Cu pillar bump
Application ‧ Graphic / GPU / APU / AP ‧ PMIC ‧ AP
‧ Chipset ‧ Wireless ‧ PMIC
‧ Wireless ‧ Audio ‧ Graphic / GPU / APU / AP
‧ FPGA ‧ Chipset
‧ Memory ‧ Wireless
‧ ASIC / PMIC ‧ FPGA
‧ RFIC ‧ ASIC / PMIC
‧ RFIC
PROCESS CAPABILITY
  Solder Bump Ball Placement Cu pillar Bump
Wafer size 12 inch / 8 inch 12 inch / 8 inch 12 inch / 8 inch
Process 1. FOC
2. REPSV
3. RDL
1. REPSV
2. RDL
1. FOC
2. REPSV
Min. bump pitch Array: 100um Array: 350um Array: 60um
Bump material 1. Eutectic
2. Sn/Ag
3. SnCu
4. SnAgCu
SnAgCu Cu/NI/SnAg Cap
RDL trace Cu Cu
Bump/Ball height Target ± 10%
Coplanarity < 20 um
Target ± 15 um
Coplanarity < 30 um
Target ± 10%
Coplanarity < 20%
Bump/Ball Diameter Target ± 10% Target ± 12 % Target ± 10%
Bump/Ball shear force Eutectic Bump : >2.0 g/mil²
Pb-free Bump : >2.5 g/mil²
>2.5 g/mil² >2.5 g/mil²
 
 
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