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SPIL's superior achievements in Reseach and Development have resulted in new technologies that will be utilized to meet future packaging demands.

3DIC Technology Cu Pillar and BOT Flip Chip Technology
3DIC is a package technology which is gathering and vertically stacking homogeneous or heterogeneous dies into Multi-Chip-Module (MCM) with Through-Silicon-Via (TSV)...   For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends. Cu pillar (+ B.O.T.) provides better substrate layout density, so it can contract package size and reduce substrate layers to lower the cost...
Thin Wafer Technology Fine Pitch Wire Bonding Technology
Wafer thinning technology has become very important as the demand for ultra-thin die used in stacked packages, IC cards and other applications are increasing...   Wire Bond Technology is still the mainstream in the manufacturing in electronic packages, and has moved toward finer pitch in response to increased demands for more I/Os in smaller spaces. SPIL now has mature capability for implementation of various kinds of fine pitch wire bonds...
Thin Molding Technology Exposed Die Molding Technology
Thin mold technology has become a very important technology, as the demand for thin packages used in compact devices, such as FCCSP, ePoP and other applications, are increasing.
Thin mold focuses on controlling mold thickness and filling the void between bumps and balls. SPIL promotes two methods, transfer mold and compression mold. Both of them are qualified by our customers and already in mass production...
  Exposed Die FCCSP is designed to provide the thinnest bonding line and best thermal impedance between the Flip Chip die backside and the attached heat sink. Molding process is the key process of exposed die FCCSP and required to be proceeded in specific film type molding equipment...
PoP Technology SiP Technology
Package on package (PoP) is an integrated circuit packaging method to combine vertically discrete logic and memory ball grid array (BGA) packages. It allows higher component density in electronic products, such as smart phones, media tablets, digital cameras, game consoles...   A System in Package (SiP) is a combination of one or more semiconductor devices plus optionally passive components that define a certain functional block within a quasi-package that is then, in turn, mounted onto the system’s main board assembly...
FO-WLP Technology Fingerprint Sensor Assembly Technology
Fan-Out Wafer Level Package (FO-WLP) has been developed to offer additional space for routing higher number of I/O on top of silicon chip area and extending the package size with so-called the fan-out process which cannot be possibly applied in conventional Fan-In Wafer Level Package (FI-WLP)...   Fingerprint sensors are one kind of biometrics used to identify individuals and verify their identities. In assembly process, it needs additional processes, such as coating, and laser cutting for singulation. The structure has wire bond LGA and Flip chip on FCCSP...
 
 
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