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Flip Chip Packages
Siliconware's Flip Chip packages provide the ideal solution for low to high I/O, high electrical performance demand in high end memory, ASICs, microprocessor applications where high frequency, high speed are required. The package offers ball counts in excess of 2597 with higher electrical performance compared to the traditional BGA package. Siliconware offers the flip chip packages both in the BGA and CSP type, and continues to develop the widest range of flip chip interconnected packages to meet customers' demand. Siliconware serves a full turn-key solution for wafer bumping, wafer sort, flip chip assembly and testing services.
Flip chip earns its name because the die is flipped directly onto the substrate. The interconnection between the die and substrate is made through an array of bumps (Figure 1) that are placed on the bonding pads of the die surface.
Changing from wire bonding to a flip chip configuration makes it possible to jump into a higher pin count, and high electrical performance applications.
Flip chip interconnections allow better electrical performance due to the shorter electrical path. The decrease from the die to substrate inductances using bumps instead of wires results in lower attenuation of high frequency and fast raise signals. The array of bumps under the chip also allows the die to shrink which reduces the wafer cost. The flip chip structure also allows you to make power and ground connections to internal points on a die, resulting in better chip performance. To increase thermal performance, optional heat spreaders can be attached on the backside of the flipped die. Thus, flip chip products are the recommendation for high speed, high thermal requirement applications.
Flip chip BGA packages are found in a variety of modern applications that demand for higher levels of electrical performance. Included are low to high-end workstations, routers and switches. Components in graphics, DSP, processors and performance ASIC devices find FCBGA package attractive.
The Flip chip CSP packages are suitable for low lead count, high frequency, high performance, and portable products such as performance memory, RFICs, and DSPs.
High speed:
Low interconnection inductance.
Low voltage:
Lowest power/ground loop inductance, power/ground pad can be routed and isolated directly in the core.
High thermal:
Heat sink can be attached directly to the die back.
High I/O:
High lead count is made possible through an array of bumps.
Customized Design:
Siliconware's strong design team is now offering a customized flip chip package design to meet customer's requirements. By combining the high quality thermal / electrical / stress simulation and tremendous assembly technologies, Siliconware can provide full customized design flip chip solutions.
Flip Chip Package Options:
Flip Chip BGA
Siliconware is now offering the Flip Chip BGA package; a flip chip solution for high performance BGA packaging. Area array flip chip bump design utilizes the die area and provides the shortest interconnection path as a replacement for conventional wire bonding. Proprietary assembly process has been developed for this novel packaging.
A fine line/space BT base laminate substrate or a blind/buried via, laser drilled build-up organic substrate can be used for Siliconware's Flip Chip BGA packages. Optional heat spreader attaching process can provide a superior heat dissipation of flip chip dies, which are suitable for high-end applications.
• 4-18 layer build up substrate
• Optional one/two piece heat spreader for high thermal requirement
• Minimum 85 µm bump pitch for solder bump and minimum 80µm for copper pillar bump
• Die size up to 27x32 mm
• Package sizes from 11x11mm to 67.5x67.5 mm
• JEDEC MS-034 compliant, 1.27/1.00/0.8/0.75/0.65/0.5/0.4 mm pitch BGA footprint
• Package up to 4344 balls
• All Flip Chip package families can meet RoHS requirements. (2005/10/25)
• Moisture Sensitivity JEDEC Level 4C
• Temp. Cycle Test -55/+125°C, 1000 cycles
• Unbiased HAST 130°C, 85% RH, 33.3 psi, 96 hours
• High Temp. Storage 150°C, 1000 hours
Note: Sample preconditioning prior to environmental tests are as follows:
Baking 125°C, 24 hours ◊ Pre-con: 30°C / 60% RH / 96 hours ◊ IR Reflow 3 times, 245/260°C
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