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Siliconware's Flip Chip packages provide the ideal solution for low to high I/O, high electrical performance demand in high end memory, ASICs, microprocessor applications where high frequency, high speed are required. Siliconware offers the flip chip packages both in the BGA and CSP type, and continues to develop the widest range of flip chip interconnected packages to meet customers' demand. Siliconware serves a full turn-key solution for wafer bumping, wafer sort, flip chip assembly and testing services.
Flip chip earns its name because the die is flipped directly onto the substrate. The interconnection between the die and substrate is made through an array of bumps that are placed on the bonding pads of the die surface.
Changing from wire bonding to a flip chip configuration makes it possible to jump into a higher pin count, and high electrical performance applications.
Flip chip interconnections allow better electrical performance due to the shorter electrical path. The decrease from the die to substrate inductances using bumps instead of wires results in lower attenuation of high frequency and fast raise signals. The array of bumps under the chip also allows the die to shrink which reduces the wafer cost. The flip chip structure also allows you to make power and ground connections to internal points on a die, resulting in better chip performance. To increase thermal performance, optional heat spreaders can be attached on the backside of the flipped die. Thus, flip chip products are the recommendation for high speed, high thermal requirement applications.
The Flip chip CSP packages are suitable for low lead count, high frequency, high performance, and portable products such as performance memory, RFICs, and DSPs.
Customized Design:
Siliconware's strong design team is now offering a customized flip chip package design to meet customer's requirements. By combining the high quality thermal / electrical / stress simulation and tremendous assembly technologies, Siliconware can provide full customized design flip chip solutions.
Flip Chip Package Options:
Flip Chip CSP
Siliconware is now offering the Flip Chip CSP package; a flip chip solution for CSP packaging. Utilizing the solder bump flip chip interconnection technology, a peripheral or array flip chip bump design provides the shortest interconnection path as a replacement for conventional wire bonding.

Based on the configuration of Siliconware's Thin and Fine-pitch BGA (TFBGA) and Quad Flat Non-lead (QFN), the packages provides an easy-to-use construction for customers. Utilizing the fine line/space, state-of-the-art ultra fine mechanical drilled thin core laminate substrate and half-etched Cu leadframe, Siliconware's Flip Chip CSP offers a cost-effective option for high electrical performance CSP solution. Optional exposed die design allows the minimum package thickness down to 0.5 mm for handheld/portable electronics.


• 2-10 layer thin organic substrate or Cu leadframe.
• Minimum 147 µm bump pitch (Solder bump)
• Minimum 50 µm bump pitch (Cu pillar bump without escape line)
• Minimum package thickness 0.5 mm (LGA, underfilled), 0.55 mm for overmolded
• Package sizes from 2.3X3.1 mm to 20x20 mm

• All Flip Chip package families can meet RoHS requirements. (2005/10/25)
• Moisture Sensitivity JEDEC Level 3
• Temp. Cycle Test -55/+125°C, 1000 cycles
• Unbiased HAST 130°C, 85% RH, 33.3 psi, 96 hours
• High Temp. Storage 150°C, 1000 hours

Note: Sample preconditioning prior to environmental tests are as follows:
Baking 125°C, 24 hours ◊ Pre-con: 30°C / 60% RH / 192 hours ◊ IR Reflow 3 times, 245/260°C

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