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Siliconware's wafer Level package is a true wafer level CSP package. Siliconware is able to provide the wafer level scale products including printing/Plated Directed LF bump(FOC), or Repassivation(RePSV) and Redistribution(RDL) with LF bumps. Through the integration, Siliconware can truly provide customers an excellent support to meet the time-to-market demands by the full turnkey service from product design, bumping, testing, to assembly, that include lapping, marking, saw and tape&reel.
APPLICATIONS
• Communication
• WLAN
• Memory storage
• Controller
FEATURES
• Available in 8 inch and 12 inch bumping wafers.
• Repassivation and Redistribution WLP with PI dielectrics.
• Backside grind and laser mark
• Ship to customer in wafer form, tape-real or chip-tray.
Process Flow Material
Normal package
Bumping
Direct bump(FOC)
1. WAFER INCOMING
2. UBM PATTERN Al(Ti)/NiV/Cu, Ti/Cu/Cu
3. BUMP FORMING LF bump
4. FINAL INSPECTION
5. SHIPPING
Repassivation(REPSV)
1. WAFER INCOMING
2. PI PATTERN PI
3. UBM PATTERN Al(Ti)/NiV/Cu, Ti/Cu/Ni
4. BUMP FORMING LF bump
5. FINAL INSPECTION
6. SHIPPING
Redistribution(RDL)
1. WAFER INCOMING
2. PI1 PATTERN PI
3. RDL PATTERN Ti/Cu/Cu, Ti/Al/Ti
4. PI2 PATTERN PI
5. BUMP FORMING LF bump
6. FINAL INSPECTION
7. SHIPPING
Post bump sort  
Backend Process
1. WAFER INCOMING
2. WAFER BACKSIDE GRIND (Option)
3. WAFER BACKSIDE LAMINATION (Option)
4. WAFER MOUNT
5. LASER GROOVING (Option)
6. WAFER SAW
7. TAPE AND REEL
8. SHIPPING
WAFER LEVEL RELIABILITY
• HAST 130°C, 85% RH, 33.3psia, 96 hours
• High Temp. Storage Life test 150°C, 500 / 1000 hours
• Multi-reflow 1/ 3/ 5/ 10/ 20 times
BOARD LEVEL RELIABILITY
• TCT -40°C~125°C, 500 cycle
• Drop Test 1mm Height,30 drops
 
 
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