SPIL

Stacked Die Family Overview

The electronics market trend is to offer more functionality, better performance, higher density, lower cost, along with smaller footprints and lower profiles. Siliconware Stacked die packages are continuously being upgraded to meet these demands. Compared to single die packages, the stacked die package combines with several different functional devices, or increases memory density within same footprints as a single die package. The Siliconware stacked die package line-up includes substrate base and lead frame base utilizing advanced assembly technologies.

What is a Stacked Die Package?

The stack die package is a technology, which stacks multiple dice vertically in the same package. For example, stacks multiple memory dice to increase memory density, or combines ASIC with memory dice.

Why use Stacked Die Package?

Increasingly more design engineers around the world have discovered working with Siliconware is the sure way to resolve their increasing demands for stacked die packaging. The stacked die package offers you multiple functionality, better performance, higher density, lower cost, along with smaller footprints and lower profiles. The stacked die package is the ideal solution for system in package applications such as wireless product, portable product, and memory card. Siliconware's extensive experience, robust infrastructure and strong R&D team allow us to share the latest technology developments with you and still provide packages with reduced turnaround times at high volumes.

Low Profile Stacked-die CSP

VTLGA / WTLGA / UTLGA / XTLGA
SVFBGA / SUTLGA (Stacked Very-Thin & Fine-pitch Ball Grid Array) / (Stacked Ultra-Thin Land Grid Array)
Siliconware's Low profile Stacked CSP implements chips vertically stacked on other chips based on the existing single die technology and infrastructure. The advent of a 3D package reduces the system board area with function integration and improved electrical performance. Siliconware stacked die CSP is the best suited for portable/handheld products where space is a concern.

APPLICACION

The Low profile Stacked CSP is a high circuit density package, which is best for Flash/SRAM and Logic/memory combinations. This technology prevails and is commonly adopted in portable products, such as wireless handsets, PDAs, cellular phones, GPS, portable computers, removable HDD and other applications, including communication satellites and internet servers.

FEATURES

• Excellent electrical performance
• Relative low cost compared with single die package
• Thin wafer with a minimum 2 mils thickness
• Small form factor / light weight
• Pb-free solder ball (Option)
• Full in-house design capability
• JEDEC standard outlines

STANDARD PROCESS FLOW AND MATERIALS

Process Flow

Material

Wafer Back Grinding

Grinding tape

Wafer Mount

Blue tape

Wafer Saw & Clean

2nd Optical Inspection

Substrate Pre-bake

Die Attach & Epoxy Cure

Non-conductive Film

Plasma Clean

Wire Bond

Gold Wire: 4N Au & 2N Au,
Copper Wire :Pd-Cu, 4N Cu

3rd Optical Inspection

Molding

Compound: Kyocera

Marking

White Ink

Post Mold Cure

Ball Placement (Option)

Sn63/37Pb ;
Sn/Ag/Cu:96.5/3/05, 95.5/4/05 & 98.5/1/05

Singulation

Tray

Final Visual Inspection

Packing

Tray