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| MPBGA Family Overview |
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Siliconware's Multi-Package BGA provides an alternative
multi-chip module solution when know-good-die, KGD, is not feasible. Multiple
chips are integrated individually after undergoing functional test within
one package form factor. Rework of package on substrate is feasible to ensure
the module yield. Siliconware is committed to offer customized design Multi-Package
BGA with full engineering support for design, assembly and testing solution.
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| What is a MPBGA Package? |
| The Multi-Package BGA package integrates different functions of chips on a substrate and connects electrical input and output to a circuit board. These chips are individually integrated after undergoing functional test within one package form factor. Siliconware's MPBGA family includes MPBGA, HS-MPBGA, MP-FCBGA, EHS-MPFCBGA and PoP. |
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| Why use a MPBGA Package? |
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The Multi-Package BGA has proven to be the most effective
packaging, which integrates currently available ICs into a smaller, more
cost-effective, single package. Specific examples of Multi-Package BGA applications
include core logic chip sets, microprocessor, micro controller systems,
and graphics cards. Areas where board density is critical will find Multi-Package
BGA packages to be the most useful packaging. Applicable markets include
laptops, sub-notebooks, telecomm, wireless, and PC cards.
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| (Multi-Package Ball Grid Array) |
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Siliconware's Multi-Package BGA provides alternative
multi-chip module solution when know-good-die, KGD is not feasible. Multiple
chips are integrated separately after the functional test using one package
in CSP form factor. Rework of CSP on substrate is feasible to ensure the
module yield. Siliconware is committed to offering customized design Multi-Package
BGA with full engineering support for design, assembly and testing solution.
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| APPLICATIONS |
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Multi-Package BGA packaging has been proven most effective
when repackaging currently available ICs into a smaller and more cost-effective
single package. Specific examples of Multi-Package BGA applications include
core logic chip sets, microprocessor, micro controller systems, and graphics
cards. Areas where board density is critical will find Multi-Package BGA
packages to be most useful. Prospective markets include laptops, sub-notebooks,
telecomm, wireless and PC cards.
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| FEATURES |
• Multiple packages in single package
• Reworkable CSP surface mount on the package
• Rigid Substrate
• Improved electrical performance
• Full in-house design capability
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| W/B version: |
| Wafer Back Grinding (Option) |
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| Wafer Mount |
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| Wafer Saw & Clean |
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| 2nd Optical Inspection |
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| Substrate Pre-bake |
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R/C SMT (Option)
Die Attach & Epoxy Cure
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Epoxy: Ablestick
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| Plasma Clean (Option) |
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| Wire Bond |
Gold Wire:
99.99% Au
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| 3rd Optical Inspection |
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Post Mold Cure
Solder ball Mount, Reflow & Flux Clean
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Sn/Pb: 63-37;
Sn/Ag/Cu: 95/4.5/0.5
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| Singulation |
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| 1st Final Visual Inspection |
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| Function Test (Option) |
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| CSP SMT |
Sn/Pb: 63-37;
Sn/Ag/Cu: 95/4.5/0.5
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2nd U/F or IR
Glue
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Cockson/Loctite |
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Heatspreader Attach
(Option)
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Ablestick |
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| 2nd Final Visual Inspection |
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| F/C version: |
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Process
Flow
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Standard Material |
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| Wafer Back Grinding (Option) |
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| Wafer Mount |
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| Wafer Saw & Clean |
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| 2nd Optical Inspection |
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| Substrate Pre-bake |
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| R/C SMT (Option) |
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Flip Chip Pick
& Place, Reflow
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Flux: Kestor |
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Underfill &
Curing
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U/F: Sumitomo |
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Solder ball Mount,
Reflow & Flux Clean
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Sn/Pb: 63-37;
Sn/Ag/Cu: 95/4.5/0.5
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| 1st Final Visual Inspection |
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| Function Test (Option) |
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| CSP SMT |
Sn/Pb: 63-37;
Sn/Ag/Cu: 95/4.5/0.5
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2nd U/F or IR
Glue
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Cockson/Loctite |
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Heatspreader Attach
(Option)
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Toshiba |
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| 2nd Final Visual Inspection |
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| W/B version: |
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RELIABILITY |
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| • Moisture Sensitivity |
JEDEC Level 3 ( 30°C / 60% RH / 192 hours) IR : 255 +5/ -0°C |
| • Temp. Cycle Test |
-55/+125°C, 1000 cycles |
| • High Temp. Storage Test |
150°C, 1000 hours |
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| F/C version: |
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RELIABILITY |
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| • Moisture Sensitivity |
JEDEC Level 4 (30°C / 60% RH / 192 hours) IR : 255 +5/-0 °C |
| • Temp. Cycle Test |
-55/+125°C, 1000 cycles |
| • High Accelerated Stress |
130°C, 85% RH, 33.3 PSI, 100 hours |
| • High Temp. Storage Test |
150°C, 1000 hours |
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| PoP (Package on Package) |
| Siliconware provides PoP solution while know-good-die (KGD) is a critical issue for SiP product cost saving. Multiple chips are packaged in CSP form factor and tested separately, then integrated vertically with package level interconnection. SPIL's PoP vertically combines discrete logic and memory packages for board space saving, lower pin count and performance enhancing. Siliconware is offering industrial designated PoP with full engineering support for design, assembly and testing solution. |
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| APPLICATIONS |
PoP has been proven the most effective SiP packaging technology to leverage the sub-system cost and feature-rich functionality product for mobile phones, PDAs, digital cameras, camcorders and MP3 players.
PoP bottom package (PBGA): mobile digital baseband processor, digital dies stacking or digital + analog baseband die stacking.
PoP top package (TFBGA): mobile memory for digital processor (flash memory/ mobile DRAM/ SRAM dies stacking)
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| FEATURES |
• Package(s) stacking on a package: top package (memory) surface mount on the bottom package (logic).
• Rigid Substrate
• Increased functionality but not increasing the form factor
• Simplified system integration
• Improved electrical performance
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| RELIABILITY |
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| • Moisture Sensitivity |
JEDEC Level 3 (30°C / 60% RH / 192 hours) IR : 255 +5/-0°C |
| • Temp. Cycle Test |
-55/+125°C, 1000 cycles |
| • High Accelerated Stress |
130°C, 85% RH, 33.3 PSI, 100 hours |
| • High Temp. Storage Test |
150°C, 1000 hours |
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