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Shrink Small Outline Package
Siliconware's Shrink Small Outline Package is a mini version of SOP. It is perfect for situations where space is a premium. Pin counts from 28 to 70 are available. The reduced footprints and fine pitch with Min. 25.0 mil enables smaller, lighter and more compact packages, while still utilizing our standard processes and materials for SOP packages.
Siliconware's SSOPs satisfy the packaging needs of a range of IC's including operational amplifiers, optoelectronics, controllers, logic, analog, memory, comparators, etc. End-products for the package include pagers, portable audio/video devices and RF devices/components.
• ”Gullwing" lead formatted and lead frame package
• 209 - 300 mil body sizes
• 28 - 56 lead counts
• Ink/Laser marking available
• Full in-house design ability
• JEDEC standard outlines
Process Flow Material
Wafer Back Grinding (Option)
Wafer Mount
Wafer Saw & Clean
2nd Optical Inspection
Die Attach Epoxy: Hitachi EN-4900GC
Epoxy Cure 150°C / 90 mins
Wire Bond Gold Wire: 99.99% Au
3rd Optical Inspection
Molding Compound:
Sumitomo 9200 Series / G700 Series
Marking White Ink / Laser
Post Mold Cure 175 +/- 5°C, min 1hr
Deflash & Trim
Solder Plating Sn/Pb : 85/15 ;
Sn/Bi : 98/2 ;
Sn : 100 (SPIL STD for Halogen free PKG.)
Forming & Singulation
Final Visual Inspection
Packing Anti-static Tube
• Moisture Sensitivity JEDEC Level 3 (30°C / 60% RH / 192 hours)
• Temp. Cycle Test -65/+150°C, 1000 cycles
• Pressure Cooker 121°C, 100% RH, 2 atm, 240 hours

Note: Sample preconditioning prior to environmental tests is as follows:
Baking 125°C, 24 hours ◊ Pre-con: 30°C / 60% RH / 192 hours ◊ IR Reflow 3 times, 260°C

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