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Wafer Bumping Services

Wafer Bumping is an advanced wafer level packaging technology which uses solder bumps to form the interconnection between the integrated circuit (IC) and the package, and it is a replacement of wire bonding technology. This technology has the benefit of high density, good thermal dissipation and good electrical performance.
SPIL provides customers with both 200mm and 300mm wafer bumping services, including printed bump, plated bump and ball placement technology with eutectic, lead free and copper pillar materials.

APPLICATIONS
  Solder Bump Ball Placement Cu pillar bump 2.5D µbump FOMCM
Application ‧ Graphic / GPU / APU ‧ PMIC ‧ AP ‧ HPC ‧ HPC
‧ Chipset ‧ Wireless ‧ PMIC ‧ IoT / Wearable ‧ IoT / Wearable
‧ Wireless ‧ Audio ‧ Graphic / GPU / APU / AP / AI
‧ FPGA ‧ Chipset
‧ Memory ‧ Wireless
‧ ASIC / PMIC ‧ FPGA
‧ RFIC ‧ ASIC
‧ RFIC
PROCESS CAPABILITY
  Solder Bump Ball Placement Cu pillar Bump 2.5D µbump FOMCM
Wafer size 12 inch / 8 inch 12 inch / 8 inch 12 inch / 8 inch 12 inch 12 inch
Process 1. FOC
2. REPSV
3. RDL
1. REPSV
2. RDL
1. FOC
2. REPSV
1. FOC ( uBump)
2. uPad + TSV reveal + C4 bump
1. uBump
2. 3RDL+uPad
3. C4 bump
Min. bump pitch Array: 100um Array: 325um Array: 60um Array: 45um Array: 40um
Bump material 1. Sn/Ag
2. SnAgCu
SnAgCu Cu/NI/SnAg Cu/NI/Cu/SnAg (uBump)
Cu/Ni/SnAg ( C4)
Cu/NI/Cu/SnAg (uBump)
Cu/NI/SnAg (C4)
RDL trace Cu Cu Cu Cu
Bump/Ball height Target ± 10%
Coplanarity < 20 um
Target ± 15 um
Coplanarity < 30 um
Target ± 10%
Coplanarity < 20%
Target ± 10%
Coplanarity < 20%
Target ± 10%
Coplanarity < 20%
Bump/Ball Diameter Target ± 10% Target ± 12 % Target ± 10% Target ± 10% Target ± 10%
Bump/Ball shear force
Pb-free Bump : >2.5 g/mil²
Solder tip >2.5 g/mil²
Cu pillar : >7 g/mil²
Solder tip >2.5 g/mil²
Cu pillar : >7 g/mil²
Pb-free Bump : >2.5 g/mil²
Solder tip >2.5 g/mil²
Cu pillar : >7 g/mil²
Pb-free Bump : >2.5 g/mil²
 
 
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