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Thin Wafer Technology Application Wafer thinning technology has become very important as the demand for ultra-thin die used in stacked packages, IC cards and other applications are increasing. • Stacked Package: Ultra thin die (Target thickness 25~50um) • IC card: Target Thickness 30~80um Risks for Wafer Thinning Study Results SPIL has developed a complete ultra-thin grinding solution that includes four key elements: 1. In-line machine system 2. Polish process 3. Protective tape 4. Tool design SPIL is continuously researching the process to ensure the best results for a variety of ultra-thin applications. Wafer Thinning Roadmap & Current Capability Technology Item Production Available 2016 2017 2018 8" / 12" Normal Wafer Thickness (um) 38 38 25 25 25  12" Normal Wafer Thickness (um) Polish(um) 38 25 25 25 25 Poligrind(um) 45 45 45 45 45 GDP(um) 38 25 25 25 25 Total Thickness Variation(um) 5 3 3 3 3  12" Bump Wafer Thickness (um) bump height: 70~110um 100 75 50 50 50 bump height: 190~250um 170 152 152 152 152 Cu pillar bump height:38~50um 70 60 40 40 40 Cu pillar bump height:51~80um 70 60 50 50 50 Total Thickness Variation(um) 10 8 5 5 5 Laser Grooving with Blade Saw Scribe Line Width (um) 60 50 50 50 50 Stealth Dicing Scribe Line Width (um) With metal layer 30 30 30 30 30 Without metal layer 30 15 10 10 10 Wafer Blade Saw Scribe line Width (um) 50 30 30 30 30

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