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Cu Pillar and BOT Flip Chip Technology
The typical bump structure of Cu pillar bump is as below; bump UBM was sputtered on PSV (SiN or PI) and Cu post with solder tip formed by plating process. The typical Cu pillar height is 50~70 um, and the typical production bump pitch is 60~125 um.
This technology can be applied on application processor, baseband, PMIC, memory devices, etc. products. For mobile communications, flip chip development is driven by increased device performance and package miniaturization trends, particularly for the CPU or so called applications processor that powers smart phones and media tablets.
• Lead free solution for RoHS requirement
• High current and EM capability(at least 3X better than LF solder bump )
• Fine pitch (high I/O density) with B.O.T. (Bump On Trace)
Higher device performance leads to more input/output connections per IC, while miniaturization requires smaller/ thinner packaging, leading to smaller, closer spaced connections.
Fine Pitch Approach – Cu Pillar
Cu pillar (+ B.O.T.) provides better substrate layout density, so it can shrink package size and reduce substrate layers (such as 6L → 4L) to lower the cost.
Example: 150um Bump pitch with 25/25um trace width/space
1.Solder bump : No trace designed in between 2 bumps.
2.Cu pillar bump + B.O.T. : Allow 2 traces designed between 2 bumps.
Substrate Trace Layout Rule
Low Cost Solution >>> Cu Pillar + BOT
Fine Pitch Solution:
TCNCP (Thermal Compression bonding Non-Conductive Paste)
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