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FO-WLP(Fan-Out Wafer Level Package) Technology
What is FO-WLP:
Fan-Out Wafer Level Package (FO-WLP) has been developed to offer additional space for routing higher number of I/O on top of silicon chip area and extending the package size with so-called the fan-out process which cannot be possibly applied in conventional Fan-In Wafer Level Package (FI-WLP).
Also, Fan-Out innovation is a key bridging technology for more advantageous extensions into 3D stacking, known as the “Next Generation” 3D integration for ultra thin profile Fan-Out Package-on-Package (FO-PoP) and high density interconnection Fan-Out Multi-Chip Module (FO-MCM) with fine line and multi layer RDL implemented.
Target Application :
• Low Pin Count Application for PMIC/ RF/ WIFI/ PA/ Audio etc.
• Mobile Application for Smart Phone & Tablet, High End AP/BB
• High-End Application for High performance computing, Networking & Data servers
Benefits :
• Small form factor & thin package (substrate-less)
• High IO / High bandwidth with fine line/multi-layer RDL routiability
• Bridging technology for embedded 3D or 3D stacking
Technology Feature :
FO-SD
• Single Die embedded in mold compound to have more IO than WLCSP by applying fan-out wafer level RDL processing.
• Thin dielectrics RDL with fine lines routing capability.
 
 
 
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